• DocumentCode
    450536
  • Title

    A Parallel PLA Minimization Program

  • Author

    Galivanche, R. ; Reddy, S.M.

  • Author_Institution
    Motorola Inc. Chandler, AZ
  • fYear
    1987
  • fDate
    28-1 June 1987
  • Firstpage
    600
  • Lastpage
    607
  • Abstract
    In this paper we report on an implementation of a parallel algorithm to minimize PLA realizations of logic functions. The algorithm is derived from a widely available PLA minimization program called ESPRESSO-MV. The parallel algorithm was implemented on a shared memory multicomputer system. In the course of development of the parallel algorithm, some changes were made to ESPRESSO-MV which resulted in lower computing time. Experimental results using 105 PLAs are included.
  • Keywords
    Automatic control; Concurrent computing; Logic functions; Microprocessors; Minimization methods; Parallel algorithms; Permission; Programmable logic arrays; Time sharing computer systems; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1987. 24th Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-8186-0781-5
  • Type

    conf

  • DOI
    10.1109/DAC.1987.203309
  • Filename
    1586293
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=450536