Title :
A Parallel PLA Minimization Program
Author :
Galivanche, R. ; Reddy, S.M.
Author_Institution :
Motorola Inc. Chandler, AZ
Abstract :
In this paper we report on an implementation of a parallel algorithm to minimize PLA realizations of logic functions. The algorithm is derived from a widely available PLA minimization program called ESPRESSO-MV. The parallel algorithm was implemented on a shared memory multicomputer system. In the course of development of the parallel algorithm, some changes were made to ESPRESSO-MV which resulted in lower computing time. Experimental results using 105 PLAs are included.
Keywords :
Automatic control; Concurrent computing; Logic functions; Microprocessors; Minimization methods; Parallel algorithms; Permission; Programmable logic arrays; Time sharing computer systems; Very large scale integration;
Conference_Titel :
Design Automation, 1987. 24th Conference on
Print_ISBN :
0-8186-0781-5
DOI :
10.1109/DAC.1987.203309
