DocumentCode
450537
Title
Improving a PLA Area by Pull-Up Transistor Folding
Author
Lursinsap, Chidchanok ; Gajski, Daniel
Author_Institution
The Center for Advanced Computer Studies, University of Southwestern Louisiana, Lafayette, LA
fYear
1987
fDate
28-1 June 1987
Firstpage
608
Lastpage
614
Abstract
The constraints limiting multiple PLA folding are the positions of pull-up transistors (Tpu) and the layout architecture which supports only I/O folding. In this paper, we present a novel architecture supporting multiple I/O, term, and pull-up foldings with through-the-cell net routing. The pull-up folding allows implementation of multiple level Boolean functions. Our architecture model achieves a better densities in comparison with PLA model.
Keywords
Boolean functions; Computer architecture; Computer science; Ducts; Filling; MOS devices; Permission; Programmable logic arrays; Routing; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1987. 24th Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0781-5
Type
conf
DOI
10.1109/DAC.1987.203310
Filename
1586294
Link To Document