DocumentCode
450566
Title
A Hardware Accelerator for Maze Routing
Author
Won, Youngju ; Sahni, Sartaj ; El-Ziq, Yacoub
Author_Institution
University of Minnesota, Mpls., MN
fYear
1987
fDate
28-1 June 1987
Firstpage
800
Lastpage
806
Abstract
A hardware accelerator for the maze routing problem is developed. This accelerator consists of three 3 stage pipelines. Banked memory is used to avoid memory read/write conflicts and obtain maximum efficiency.
Keywords
Lee´s router; Maze routing; hardware solutions; Design automation; Hardware; Labeling; Logic; Parallel architectures; Permission; Pipelines; Read-write memory; Routing; Wire; Lee´s router; Maze routing; hardware solutions;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1987. 24th Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0781-5
Type
conf
DOI
10.1109/DAC.1987.203340
Filename
1586324
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