DocumentCode :
450574
Title :
Gate Matrix Layout Synthesis with Two-Dimensional Folding
Author :
Lin, Ichiang ; Du, David H C ; Yen, Steve H C
Author_Institution :
Department of Computer Science, University of Minnesota, Minneapolis, MN
fYear :
1989
fDate :
25-29 June 1989
Firstpage :
37
Lastpage :
42
Abstract :
We have developed a gate matrix layout synthesis tool which utilizes folding technique on both rows and columns. The conventional interval graph model and the recently proposed dynamic net-list representation can not fully depict circuit schematics such as inter-net connections. The incomplete representations may mislead the search process for an optimal solution during the layout partitioning and the gate ordering phases. We propose a new graph-based model called hierarchical dynamic net-list to improve the schematic representation. Based on the new model, the folded layout area in the partitioning phase can be more accurately estimated. The new gate ordering algorithm proposed by us also takes the advantages of the hierarchical dynamic net-list model to handle the gate placement in the folded layouts. The experimental results show 12% to 15% improvement in layout area for small circuits and 30% improvement for a large circuit.
Keywords :
Circuit synthesis; Computer science; Integrated circuit interconnections; MOS devices; MOSFETs; Matrix decomposition; Partitioning algorithms; Phase estimation; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1989. 26th Conference on
ISSN :
0738-100X
Print_ISBN :
0-89791-310-8
Type :
conf
DOI :
10.1109/DAC.1989.203366
Filename :
1586350
Link To Document :
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