Abstract :
As integrated circuit technologies provide ever-decreasing clock cycle times, the demands of CAD systems for the verification and automated design of both chips and packages have changed. In particular, physical design tools must include complex delay constraints along with the more traditional area constraints. In addition, new packaging technologies such as silicon-on-silicon, require CAD tools that can take into account complex transmission line and coupling effects and increasingly critical power supply distribution and noise problems. In this panel, a group of system designers who are working with high performance technologies including CMOS, gallium arsenide, and bipolar structures will describe the problems they face using existing CAD technology. The panelists have been encouraged to present their design problems as a challenge to the design automation community for a new generation of design aids.
