Abstract :
The contribution of packaging to circuit performance is becoming increasingly important. In high-speed computer systems, performance and density limits are being set more by interconnect and packaging constraints than by transistor switching speed. Multi-chip, silicon-on-silicon hybrid packages can significantly improve performance by eliminating a level of packaging. In this tutorial, a variety of approaches to advance multi-chip packaging techniques will be presented. In particular, a system will be presented that can achieve a factor of five to eight improvement in volume and a factor of two speed improvement.
