Automatic Layout of Silicon-On-Silicon Hybrid Packages

In modern, high speed computer systems, performance and density limits are being set more by interconnection and packaging constraints than by transistor characteristics. The most severe limitation comes from the single-chip packages that carry the VLSI circuits. Multichip, silicon-on-silicon hybrid packages can significantly improve performance by eliminating this level of packaging. A system has been developed to automatically generate hybrid layouts given a schematic description and layouts of the VLSI circuits. This paper describes the hybrid technology, the design automation system foundation, and the hybrid layout system. This layout method, in combination with the fabrication technology, produces layouts that are 5 to 8 times more dense than the same circuits implemented with single-chip packages on printed circuit boards. Simulations show that clock speeds can be increased by a factor of two.