DocumentCode :
450650
Title :
Worst-Case Delay Estimation of Transistor Groups
Author :
Gaiotti, Serge ; Dagenais, Michel R. ; Rumin, Nicholas C.
Author_Institution :
Dept. of Electrical Engineering, McGill University, Montreal, Quebec, Canada
fYear :
1989
fDate :
25-29 June 1989
Firstpage :
491
Lastpage :
496
Abstract :
This paper presents two algorithms for performing worst-case delay estimation using transistor-level timing simulation techniques. The first algorithm, Dynamic Path Selection (DPS), determines in linear time the slowest paths in series-parallel transistor groups; the exponential complexity remains for transistor groups with bridges. The second algorithm, Delay Subnetwork Enumeration (DSE), complements the DPS method by taking into account logic dependencies within transistor groups. The two methods are combined in the static timing analyzer TAMIA, to provide accurate worst-case delay estimation of digital CMOS circuits.
Keywords :
Bridge circuits; CMOS digital integrated circuits; CMOS logic circuits; Delay estimation; Driver circuits; Heuristic algorithms; Logic gates; Permission; Propagation delay; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1989. 26th Conference on
ISSN :
0738-100X
Print_ISBN :
0-89791-310-8
Type :
conf
DOI :
10.1109/DAC.1989.203446
Filename :
1586430
Link To Document :
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