REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures

This paper presents a new approach to module generation. It is based on the observation that a function, realized by a module instance (e.g. a 16-bit multiplier) when restricted to a sub-function, can be realized by a reduction of the instance to a sub-instance (e.g. a 8-bit multiplier). This reduction is performed automatically by REDUSA. It offers important advantages in both the construction and verification aspects of module generators.