Title :
Loop Optimization in Register-Transfer Scheduling for DSP-Systems
Author :
Goossens, Gert ; Vandewalle, Joos ; Man, Hugo De
Author_Institution :
IMEC Laboratory, Leuven, Belgium
Abstract :
In this paper, we discuss a control-flow transformation called loop folding, during the scheduling of register-transfer code for DSP-systems. Loop folding is functionally equivalent to data-path pipelining. An iterative loop-folding procedure, implemented in the CATHEDRAL II compiler, is presented. This technique may significantly improve the utilization of parallel hardware, available in a data path.
Keywords :
Compaction; Concurrent computing; Digital signal processing; Hardware; Laboratories; Parallel processing; Permission; Pipeline processing; Signal synthesis; Throughput;
Conference_Titel :
Design Automation, 1989. 26th Conference on
Print_ISBN :
0-89791-310-8
DOI :
10.1109/DAC.1989.203521
