DocumentCode
45102
Title
Application of VRS Methodology for the Statistical Assessment of BTI in MG/HK CMOS Devices
Author
Kerber, Andreas ; Cartier, E.
Author_Institution
IBM Res. Alliance, GlobalFoundries Inc., Yorktown Heights, NY, USA
Volume
34
Issue
8
fYear
2013
fDate
Aug. 2013
Firstpage
960
Lastpage
962
Abstract
Variability induced by bias temperature instability is an increasing concern in aggressively scaled CMOS technologies. To assess the stochastic nature of the instability, we demonstrate that the recently introduced voltage ramp stress methodology properly captures the variance component and thus can be used to study stochastic effects related to transistor design and gate-stack processes.
Keywords
CMOS integrated circuits; high-k dielectric thin films; integrated circuit reliability; stochastic processes; thermal stability; CMOS devices; bias temperature instability; gate-stack processes; high-k CMOS; metal gate CMOS; stochastic nature; transistor design; variability; variance component; voltage ramp stress methodology; CMOS integrated circuits; CMOS technology; High K dielectric materials; Logic gates; Reliability; Stochastic processes; Stress; Bias temperature instability; CMOS devices; high-k dielectrics; metal gate; variability; voltage ramp stress (VRS);
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2013.2268050
Filename
6560365
Link To Document