DocumentCode :
451865
Title :
Technology Mapping for Low Power
Author :
Tiwari, Vivek ; Ashar, Pranav ; Malik, Sheard
Author_Institution :
Dept. of EE, Princeton Univ
fYear :
1993
fDate :
14-18 June 1993
Firstpage :
74
Lastpage :
79
Abstract :
The last couple of years have seen the addition of a new dimension in the evaluation of circuit quality - its power requirements. Low power circuits are emerging as an important application domain, and synthesis for low power is demanding attention. The research presented in this paper addresses one aspect of low power synthesis. It focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric. Several issues in modeling and measuring circuit power, as well as algorithms for technology mapping for low power are presented here. Empirically, it is observed that a significant variation in the power consumption is possible just by varying the choice of gates. Technology mapping for low power provides circuits with up to 24% lower power requirements than those obtained by technology mapping for area.
Keywords :
Automatic logic units; Circuit synthesis; Delay; Energy consumption; Libraries; Logic design; Logic devices; National electric code; Power measurement; Vegetation mapping;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1993. 30th Conference on
ISSN :
0738-100X
Print_ISBN :
0-89791-577-1
Type :
conf
DOI :
10.1109/DAC.1993.203922
Filename :
1600195
Link To Document :
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