DocumentCode :
451878
Title :
Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits
Author :
Dharchoudhury, A. ; Kang, S.M.
Author_Institution :
Department of Electrical and Computer Engineering, Beckman Institute and Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, IL
fYear :
1993
fDate :
14-18 June 1993
Firstpage :
154
Lastpage :
158
Abstract :
This paper describes a new technique to design circuits such that the variability of the circuit performances due to device parameter fluctuations meets specifications for all values of the environmental parameters (such as operating temperature or voltage supply). The worst-case value of the performance variability is minimized and specifications on the nominal value of the performance measure are handled simultaneously. Response surface models are used to provide efficient and accurate estimates for the performance values and variability during the optimization. This technique has been successfully applied to significantly increase the parametric yields of a BiCMOS voltage-to-current converter circuit and a CMOS clock driver circuit.
Keywords :
BiCMOS integrated circuits; Clocks; Fluctuations; Minimization; Performance evaluation; Response surface methodology; Semiconductor device modeling; Temperature; Very large scale integration; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1993. 30th Conference on
ISSN :
0738-100X
Print_ISBN :
0-89791-577-1
Type :
conf
DOI :
10.1109/DAC.1993.203937
Filename :
1600210
Link To Document :
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