DocumentCode :
451881
Title :
Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization
Author :
Pullela, Satyamurthy ; Menezes, Noel ; Pillage, Lawrence T.
Author_Institution :
Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX
fYear :
1993
fDate :
14-18 June 1993
Firstpage :
165
Lastpage :
170
Abstract :
Recognizing that routing constraints and process variations make non-zero skew inevitable, this paper describes a novel methodology for constructing reliable low-skew clock trees. The algorithm efficiently calculates clock-tree delay sensitivities to achieve a target delay and a target skew. Moreover, the sensitivities also show that wires should be widened as opposed to lengthened to reduce skew since the former improves reliability while the latter reduces it. This paper introduces the concept of designing reliable clock nets with process-insensitive skew.
Keywords :
Capacitance; Clocks; Delay; Digital systems; Hardware; Pins; Pipelines; Routing; Very large scale integration; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1993. 30th Conference on
ISSN :
0738-100X
Print_ISBN :
0-89791-577-1
Type :
conf
DOI :
10.1109/DAC.1993.203940
Filename :
1600213
Link To Document :
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