Experiences in Functional Validation of a High Level Synthesis System

The goal of functional validation of a high-level synthesis system is to assert, with a reasonable degree of confidence, that the layouts generated by the high-level synthesis system correctly implement the specified behavior. This paper presents a systematic approach to functional validation based on the analysis of specification language constructs, design example formation to cover combinations of constructs, test-bench generation and automated test result comparison. We have successfully applied this approach in validating a high-level synthesis system, called DSS, which accepts specifications stated in VHDL. This effort resulted in the development of a functional validation suite consisting of 23 design examples.