Performance Directed Technology Mapping for Look-Up Table Based FPGAs

In this paper we present a new approach to performance optimized mapping for Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs). Our approach is to first perform area efficient level reductions and then reinforce these by minimizing wirelengths using timing driven placement. Experimental results indicate that our approach produces designs that have upto 12% fewer levels, 48% fewer LUTs, and 39% fewer connections compared to other approaches [2] [4]. These designs when placed using APR [6] were on the average 20% faster compared to those mapped using XNFMAP [6]. These designs when placed using APR [6] with the constraints that were generated by our timing driven placer were on the average 31% faster compared to those produced by XNFMAP [6].