DocumentCode
451895
Title
A Cost-Based Approach to Partial Scan
Author
Parikh, Prashant S. ; Abramovici, Miron
Author_Institution
AT&T Bell Laboratories, Naperville, IL; Illinois Institute of Technology, Chicago, IL
fYear
1993
fDate
14-18 June 1993
Firstpage
255
Lastpage
259
Abstract
In this paper, we present a new method for selecting flip-flops for partial scan. Our method ranks all flip-flops based on a sensitivity analysis that determines the improvement in the testability of the circuit as a result of scanning a flip-flop. Testability is computed with respect to a given set of target faults. Our method can estimate the number of scan flip-flops needed to reach a good fault coverage.
Keywords
Automatic test pattern generation; Circuit faults; Circuit testing; Costs; Electrical fault detection; Fault detection; Flip-flops; Pipelines; Sensitivity analysis; Sequential analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1993. 30th Conference on
ISSN
0738-100X
Print_ISBN
0-89791-577-1
Type
conf
DOI
10.1109/DAC.1993.203955
Filename
1600228
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