DocumentCode
451908
Title
An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition
Author
Chatterjee, Abhijit ; Roy, Rabindra K.
Author_Institution
School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA
fYear
1993
fDate
14-18 June 1993
Firstpage
343
Lastpage
348
Abstract
Most behavioral synthesis tools perform limited architectural transformations to optimize hardware. In this paper, we present a new architectural transformation scheme that changes the circuit interconnections and the descriptions of constant multipliers. The scheme is based on numerical matrix transformation algorithms that allow a given matrix to be expressed as the product of several matrices and achieves significant hardware savings over conventional methods.
Keywords
Circuit synthesis; Control system synthesis; Digital systems; Equations; Flow graphs; Hardware; High level synthesis; Integrated circuit interconnections; Signal processing algorithms; Silicon compiler;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1993. 30th Conference on
ISSN
0738-100X
Print_ISBN
0-89791-577-1
Type
conf
DOI
10.1109/DAC.1993.203972
Filename
1600245
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