Title :
An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition
Author :
Chatterjee, Abhijit ; Roy, Rabindra K.
Author_Institution :
School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA
Abstract :
Most behavioral synthesis tools perform limited architectural transformations to optimize hardware. In this paper, we present a new architectural transformation scheme that changes the circuit interconnections and the descriptions of constant multipliers. The scheme is based on numerical matrix transformation algorithms that allow a given matrix to be expressed as the product of several matrices and achieves significant hardware savings over conventional methods.
Keywords :
Circuit synthesis; Control system synthesis; Digital systems; Equations; Flow graphs; Hardware; High level synthesis; Integrated circuit interconnections; Signal processing algorithms; Silicon compiler;
Conference_Titel :
Design Automation, 1993. 30th Conference on
Print_ISBN :
0-89791-577-1
DOI :
10.1109/DAC.1993.203972
