• DocumentCode
    451919
  • Title

    A Compaction Method for Full Chip VLSI Layouts

  • Author

    Dao, Joseph ; Matsumoto, Nobu ; Hamai, Tsuneo ; Ogawa, Chusei ; Mori, Shojiro

  • Author_Institution
    Semiconductor Device Engineering Lab., Toshiba Corporation, Kawasaki, Japan
  • fYear
    1993
  • fDate
    14-18 June 1993
  • Firstpage
    407
  • Lastpage
    412
  • Abstract
    An algorithm independent layout compaction method for full chip layouts is proposed. The partitioning compaction method cuts up a large layout, compacts each block independently and then merges them to give the final compacted layout. A 16-bit CPU core (28.8K transistors) layout was compacted on a standard workstation using this method. Both the computer memory usage and processing time were reduced. Parallel processing is possible to further speed up the computation.
  • Keywords
    Compaction; Concurrent computing; Design automation; Microelectronics; Parallel processing; Partitioning algorithms; Semiconductor devices; Systems engineering and theory; Very large scale integration; Workstations;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1993. 30th Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-577-1
  • Type

    conf

  • DOI
    10.1109/DAC.1993.203983
  • Filename
    1600256
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=451919