NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits

A test generation procedure for path delay faults is proposed, that targets all path delay faults in the circuit-under-test. The procedure overcomes the difficulties in handling the exorbitant numbers of path delay faults in practical circuits by using a non-enumerative method of considering faults, i.e., it never explicitly targets any specific path delay fault. Experimental results demonstrate the effectiveness of the method in deriving tests to detect very large numbers of path delay faults in short run times.