TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry

TIM is a versatile and efficient tool for verifying and optimizing the timing of two-phase, level-clocked circuitry. TIM performs a variety of functions, such as timing verification, clock tuning, retiming for maximum speed of operation, retiming for minimum number of latches, and sensitivity analysis. In this paper, we present new polynomial-time optimization algorithms for retiming and sensitivity analysis, and we describe the implementation of the new and previously reported algorithms in TIM. We also present empirical results from the application of TIM to sequential circuitry obtained from academic and industrial sources. Our experiments show that the number of latches in edge-triggered designs which have been retimed for maximum performance can be substantially reduced in corresponding two-phase, level-clocked designs that operate at the same speed.