DocumentCode :
451990
Title :
A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules
Author :
De Jong, Gjalt G. ; Lin, Bill
Author_Institution :
IMEC, Leuven, Belgium
fYear :
1994
fDate :
6-10 June 1994
Firstpage :
49
Lastpage :
55
Abstract :
Current asynchronous tools are focussed mainly on the design of a single interface module. In many applications, one must design interacting interface modules that potentially communicate in complex and intricate ways. When designing communicating asynchronous modules, several difficult problems arise. First, even if each individual module can be synthesized correctly, according to the environmental assumptions specified for that module, the composition of the communicating modules may not work properly. Thus, one needs to have a way to model how the modules interact with each other, and to verify that their cooperation is consistent. In addition, means should be provided for communication and synchronization at a level higher than signal transitions, and for exploiting the communicating nature of these modules in optimization. This paper proposes a communicating Petri net model for describing communicating asynchronous modules. Each module is modeled by means of a labeled Petri net that extends the widely used Signal Transition Graph model by providing an abstract synchronization mechanism based on rendez-vous semantics. This enables the designer to specify high-level communication as well as low-level details such as signal transitions. Abstract synchronization events are expanded automatically to low-level handshake signals. We have developed a new algebra for communicating Petri nets that is applicable to general Petri nets, involves no unfolding, and defines hiding as generalized net contraction. We have developed methods based on this formal algebra that can be used to manipulate communicating interface modules, to verify their consistency, and to use them as a basis for optimizations.
Keywords :
Digital signal processing; Field programmable gate arrays; Hardware; Optimization methods; Petri nets; Signal design; Software systems; System buses; System-level design; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1994. 31st Conference on
ISSN :
0738-100X
Print_ISBN :
0-89791-653-0
Type :
conf
DOI :
10.1109/DAC.1994.204072
Filename :
1600345
Link To Document :
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