Interface Timing Verification with Application to Synthesis

A fundamental timing analysis problem in the verification and synthesis of interface logic circuitry is the determination of allowable time separations, or skews between interface events, given timing constraints and circuit propagation delays. These skews are used to verify timing properties and determine allowable propagation delays for logic synthesis. This paper presents an algorithm that provides tighter skew bounds with better asymptotic running time than previous methods, and shows how to apply the method to synthesis tasks.