A Global Router Optimizing Timing and Area for High-Speed Bipolar LSI´s

A timing-driven global routing algorithm applicable to high-speed bipolar LSI´s is proposed. Path-based timing constraints are directly modeled and routing paths are selected using novel heuristic criteria to minimize area as well as to satisfy the timing constraints by keeping track of the critical path delay and channel densities. Using bipolarspecific features, this router can be applied to Gbit/s LSI´s. Experimental results shows that the average delay improvement was 17.6% and the algorithm is quite promising.