Title :
DFBT: A Design-for-Testability Method Based on Balance Testing
Author :
Chakrabarty, Krishnendu ; Hayes, John P.
Author_Institution :
Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI
Abstract :
We present design for balance testability (DFBT), a systematic signature-based method for enhancing the testability of logic circuits. DFBT employs balance testing and guarantees 100% coverage of single stuck-line faults, as well as many multiple stuck-line and bridging faults. The logic overhead of DFBT is modest|only one extra I/O pin and a small number of extra gates|and the original circuit need not be altered. We illustrate DFBT by applying it to representative logic circuits.
Keywords :
Automatic testing; Circuit faults; Circuit testing; Combinational circuits; Counting circuits; Design for testability; Design methodology; Logic circuits; Logic testing; System testing;
Conference_Titel :
Design Automation, 1994. 31st Conference on
Print_ISBN :
0-89791-653-0
DOI :
10.1109/DAC.1994.204125
