DocumentCode :
452052
Title :
Random Generation of Test Instances for Logic Optimizers
Author :
Iwama, Kazuo ; Hino, Kensuke
Author_Institution :
Department of Computer Science and Communication Engineering, Kyushu University, Fukuoka, Japan
fYear :
1994
fDate :
6-10 June 1994
Firstpage :
430
Lastpage :
434
Abstract :
The attempt of using random test circuits for evaluating the performance of logic optimizers like SIS is apparently new. To generate "reasonable" random circuits, we propose the random applications of several transformation rules to an initial circuit instead of the obvious method, random placement of connections. A preliminary experiment has been conducted on SIS\´s responses against such random circuits. SIS shows considerably different performances for different circuits generated from the same original circuit.
Keywords :
Automatic testing; Design automation; Design optimization; Distributed computing; Logic design; Logic testing; Machinery; Materials testing; Permission;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1994. 31st Conference on
ISSN :
0738-100X
Print_ISBN :
0-89791-653-0
Type :
conf
DOI :
10.1109/DAC.1994.204140
Filename :
1600413
Link To Document :
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