Boolean Matching of Sequential Elements

In most logic synthesis systems, technology mapping to a target technology is performed using structural matching techniques. Recently there has been a lot of interest on the usage of boolean techniques to do matching of combinational logic. In this paper, we present an extension of boolean matching to perform technology mapping of sequential elements. The new technique is capable of recognizing the presence of complex sequential elements including JK flip-flops, multiplexed flip-flops, flip-flops with asynchronous behavior and complex latches. The underlying algorithm uses a notion of "timed" variables and relies on a fast boolean matching technique to achieve efficiency. We have implemented these ideas in a simple technology mapper and contrast the results with two other sequential mapping techniques.