A New Architecture of Built-In Self-Test for Analog-to-Digital Converters

This paper presents a built-in self-test (BIST) architecture for testing high speed analog-to-digital converters (ADCs) with sampling rates in excess of 1 GHz. A methodology for performing mixed-mode BIST simulations is proposed along with hardware architecture for performing on-chip BIST. The architecture presented utilizes an on-chip ROM and allows for the generation of test signals with multiple frequencies as well as single frequency signals. The issues associated with BIST signal generation for low voltage ADCs are also discussed