A New Architecture of Built-In Self-Test for Analog-to-Digital Converters

Author

Wibbenmeyer, Jason ; Chen, Chien-In Henry

Author_Institution

Dept. of Electr. Eng., Wright State Univ., Dayton, OH

Volume

1

fYear

2005

fDate

16-19 May 2005

Firstpage

184

Lastpage

189

Abstract

This paper presents a built-in self-test (BIST) architecture for testing high speed analog-to-digital converters (ADCs) with sampling rates in excess of 1 GHz. A methodology for performing mixed-mode BIST simulations is proposed along with hardware architecture for performing on-chip BIST. The architecture presented utilizes an on-chip ROM and allows for the generation of test signals with multiple frequencies as well as single frequency signals. The issues associated with BIST signal generation for low voltage ADCs are also discussed

Keywords

analogue-digital conversion; built-in self test; high-speed integrated circuits; integrated circuit testing; BIST signal generation; built-in self-test architecture; high speed analog-to-digital converters; mixed-mode BIST simulation; on-chip ROM; Analog-digital conversion; Built-in self-test; Circuit testing; Clocks; Frequency; Hardware design languages; Probes; Pulse generation; Read only memory; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference, 2005. IMTC 2005. Proceedings of the IEEE

Conference_Location

Ottawa, Ont.

Print_ISBN

0-7803-8879-8

Type

conf

DOI

10.1109/IMTC.2005.1604096

Filename

1604096