• DocumentCode
    45314
  • Title

    Formal Verification and Synthesis for Discrete-Time Stochastic Systems

  • Author

    Lahijanian, Morteza ; Andersson, Sean B. ; Belta, Calin

  • Author_Institution
    Dept. of Mech. Eng., Boston Univ., Boston, MA, USA
  • Volume
    60
  • Issue
    8
  • fYear
    2015
  • fDate
    Aug. 2015
  • Firstpage
    2031
  • Lastpage
    2045
  • Abstract
    Formal methods are increasingly being used for control and verification of dynamic systems against complex specifications. In general, these methods rely on a relatively simple system model, such as a transition graph, Markov chain, or Markov decision process, and require abstraction of the original continuous-state dynamics. It can be difficult or impossible, however, to find a perfectly equivalent abstraction, particularly when the original system is stochastic. Here we develop an abstraction procedure that maps a discrete-time stochastic system to an Interval-valued Markov Chain (IMC) and a switched discrete-time stochastic system to a Bounded-parameter Markov Decision Process (BMDP). We construct model checking algorithms for these models against Probabilistic Computation Tree Logic (PCTL) formulas and a synthesis procedure for BMDPs. Finally, we develop an efficient refinement algorithm that reduces the uncertainty in the abstraction. The technique is illustrated through simulation.
  • Keywords
    Markov processes; control engineering computing; control system synthesis; discrete time systems; formal verification; stochastic systems; trees (mathematics); BMDP; BMDP synthesis procedure; IMC; Markov chain; Markov decision process; PCTL formula; abstraction procedure; bounded-parameter Markov decision process; continuous-state dynamics; discrete-time stochastic system synthesis; dynamic systems control; dynamic systems verification; formal verification; interval-valued Markov chain; model checking algorithms; probabilistic computation tree logic; refinement algorithm; transition graph; Markov processes; Model checking; Probabilistic logic; Probability distribution; Stochastic systems; Switches; Finite abstraction; Markov abstraction; PCTL; formal synthesis; formal verification; model checking; stochastic systems; temporal logics;
  • fLanguage
    English
  • Journal_Title
    Automatic Control, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9286
  • Type

    jour

  • DOI
    10.1109/TAC.2015.2398883
  • Filename
    7029024