The RSFQ test-timing model for delay insensitive data processing pipeline design

A novel asynchronous RSFQ digital circuit model, test-timed RSFQ digital model (TT) is proposed in this paper. With this asynchronous approach, data is transferred in a delay-insensitive fashion to avoid the problems aroused from the global clock distribution and the timing uncertainty. In the TT model, the timing pulse to the logic module will be generated with a test logic module, instead of the time delay module, which should be necessary in most asynchronous circuits. The elimination of the delay module can basically solve the timing uncertainty bothered in the RSFQ digital system layouts. The transient simulations and logic simulations have been made for the OR module and a RSFQ data processing pipeline based on the TT scheme has been designed. The logic simulations have also been made for this pipeline, and the results showed its feasibility and satisfaction for the RSFQ digital system applications.