Title :
An ASIC design of a novel pipelined and parallel sorting accelerator for a multiprocessor-on-a-chip
Author :
Tabrizi, Nozar ; Bagherzadeh, Nader
Author_Institution :
Dept. of Electr. & Comput. Eng., Kettering Univ., Flint, MI
Abstract :
We introduce a pipelined and parallel sorting algorithm, with the time, logic, and memory complexity of O(n), O(radicn) and O(n), respectively. We then model, verify, and synthesize this unconditional algorithm for 4k-word clusters as an ASIC accelerating, plug-in engine tailored to MaRS, a multiprocessor-on-a-chip that we have recently developed; so that this engine may replace any of the processing elements (PEs) in MaRS, and provide the other PEs with an efficient sort function, using the same network protocol based on which inter-PE communication is carried out
Keywords :
computational complexity; integrated circuit design; multiprocessing systems; pipeline processing; sorting; system-on-chip; ASIC accelerating; ASIC design; MaRS; inter-PE communication; logic complexity; memory complexity; multiprocessor-on-a-chip; network protocol; parallel sorting accelerator; pipelined sorting accelerator; plug-in engine; time complexity; unconditional algorithm; Acceleration; Application specific integrated circuits; Clustering algorithms; Communication channels; Engines; Logic; Mars; Network synthesis; Protocols; Sorting;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611246
