Title :
An optimization of VLSI architecture for DFE used in Ethernet
Author :
Xuejing, Wang ; Fan, Ye ; Junyan, Ren
Author_Institution :
State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
An optimum design of decision feedback equalizer (DFE) used in Ethernet is presented. This paper proposes two improving measures for physical implementation - the hybrid form and the coefficient updating unit sharing. According to the results of synthesis using SMIC, 0.18μm CMOS process, the speed, area and power consumption of the improved DFE is optimized by 16%, 36% and 39% compared with the transposed form implementation.
Keywords :
CMOS analogue integrated circuits; VLSI; circuit optimisation; decision feedback equalisers; integrated circuit design; local area networks; 0.18 micron; CMOS process; DFE; Ethernet; SMIC; VLSI architecture; decision feedback equalizer; power consumption; Added delay; Attenuation; CMOS process; Decision feedback equalizers; Energy consumption; Ethernet networks; Intersymbol interference; Iron; Physical layer; Very large scale integration;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611261
