• DocumentCode
    453627
  • Title

    SLCAO: an effective system level communication architectures optimization methodology for system-on- chips

  • Author

    Niu, Yawen ; Bian, Jinian ; Wang, Haili ; Tong, Kun ; Zhu, Liang

  • Author_Institution
    Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing
  • Volume
    1
  • fYear
    2005
  • fDate
    24-0 Oct. 2005
  • Firstpage
    33
  • Lastpage
    36
  • Abstract
    This paper proposes an effective system level communication architectures optimization (SLCAO) methodology to optimize the on-chip communication architectures (OCAs). SLCAO methodology divides the OCAs architecting into two steps: OCAs generation and OCAs optimization, and presents some valid bus mergence strategies to enhance the system performance and decrease the system cost from hierarchical buses through the analysis of the bus load. The methodology takes into account two categories of delay models, system delay model and PE-PE delay model, to evaluate the system performance and control the optimization process. The effectiveness of SLCAO methodology is illustrated by the 10-PEs example
  • Keywords
    computer architecture; delays; system buses; system-on-chip; OCA generation; OCA optimization; PE-PE delay model; SLCAO method; bus mergence strategies; on-chip communication architectures; system delay model; system level communication architecture optimization method; system-on-chip; Character generation; Computer architecture; Control system synthesis; Cost function; Delay systems; Hardware; Optimization methods; Performance analysis; System performance; System-on-a-chip; OCA; bus mergence; communication synthesis; hierarchical buses; optimization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2005. ASICON 2005. 6th International Conference On
  • Conference_Location
    Shanghai
  • Print_ISBN
    0-7803-9210-8
  • Type

    conf

  • DOI
    10.1109/ICASIC.2005.1611263
  • Filename
    1611263