SoC design environment with automated configurable bus generation for rapid prototyping

It is important in SoC design that the design and verification can be done easily and quickly. And RT-level simulation in verification methods is still necessary, but the usage is limited by its slow speed. Therefore we propose a SoC verification environment in which hardware parts are accelerated in FPGA and cores are modeled with ISS. To connect ISS in high abstraction level with emulator in pin-level accuracy, bus functional model (BFM) is used. For hardware debugging, bus monitor is designed. By post-processing the data obtained by bus monitoring, debugging and performance estimation are possible. For easy and quick design and verification, we developed a tool which creates configurable bus architectures automatically. With this, the design time from specification to FPGA based prototyping can be reduced remarkably. Thus fast verification and design space exploration are possible. AMBA is chosen as the SoC bus protocol.