• DocumentCode
    453632
  • Title

    Challenges in PowerPC440-FS soft core development: timing perspective

  • Author

    Biggs, Terry ; Umino, Ken ; Shi, Kaijian

  • Author_Institution
    Hewlett-Packard Co., Palo Alto, CA
  • Volume
    1
  • fYear
    2005
  • fDate
    24-0 Oct. 2005
  • Firstpage
    86
  • Lastpage
    89
  • Abstract
    This paper described timing perspective challenges in PowerPC440 soft core development and provided solutions. Various micro architectures and memory implementations have been explored, and physical synthesis strategies and clock skew management have been developed to meet the challenging speed target
  • Keywords
    cache storage; clocks; microprocessor chips; timing; PowerPC440-FS; clock skew management; memory implementations; micro architectures; physical synthesis strategies; soft core development; timing perspective; Clocks; Foundries; Logic design; Memory architecture; Memory management; Microprocessors; Registers; Softening; Throughput; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2005. ASICON 2005. 6th International Conference On
  • Conference_Location
    Shanghai
  • Print_ISBN
    0-7803-9210-8
  • Type

    conf

  • DOI
    10.1109/ICASIC.2005.1611274
  • Filename
    1611274
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=453632