Title :
Design of a high-speed low-power CAM
Author :
Gu, Canghai ; Zhu, Hefei ; Zhou, Hiaofang ; Min, Hao ; Zhou, Dian
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai
Abstract :
A low power content addressable memory is presented in this paper. Two-stage comparison is used to get good performance in TLB and the best low power structure is put forward based on the power model. Lower voltage swing is also applied to reduce the power dissipation. This circuit is implemented in 0.18 mum 1P6M CMOS process. Simulation results indicate that it only consumes 4.59 muw/bit with the maximum delay of 0.983 ns in a 64-entry TLB
Keywords :
CMOS memory circuits; content-addressable storage; high-speed integrated circuits; integrated circuit design; low-power electronics; 0.18 micron; CMOS process; TLB; content addressable memory; high-speed CAM; low-power CAM; Application specific integrated circuits; Associative memory; CADCAM; Computer aided manufacturing; Delay; Laboratories; Power dissipation; Power system modeling; Semiconductor device modeling; Voltage;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611281
