Title :
A dual-symbol coding arithmetic coder architecture design for high speed EBCOT coding engine in JPEG2000
Author :
Zhang, Yi-Zhen ; Xu, Chao ; Chen, Liang-Bin
Author_Institution :
National Lab. on Machine Perception, Peking Univ., Beijing
Abstract :
This paper presents a flexible dual-symbol coding arithmetic coder (MQ coder) architecture design for the parallel coding engines of embedded block coding with optimization truncation (EBCOT) tier-1 in JPEG2000. The flexible MQ coder (FMQ) can encode two symbols simultaneously per clock cycle by using the optimized combination method. It increases the throughput rate of the arithmetic coding, which can match the high throughput rate of the parallel context modeling modules. Experimental results show that one FMQ are able to handle two bit-planes/data-pairs for the bit-plane parallel EBCOT coding engine, and the computation time is decreased about 24% compared with the engine by using the regular MQ coder
Keywords :
block codes; codecs; digital arithmetic; digital signal processing chips; high-speed integrated circuits; image coding; integrated circuit design; JPEG2000; arithmetic coding; bit-plane parallel EBCOT coding engine; dual-symbol coding arithmetic coder architecture; embedded block coding; high speed EBCOT coding engine; optimization truncation tier-1; optimized combination method; parallel coding engines; Arithmetic; Clocks; Context modeling; Discrete wavelet transforms; Engines; IEC standards; Image coding; Optimization methods; Throughput; Transform coding;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611315
