A novel clock and data recovery scheme based on sigma-delta quantization

This paper proposes a novel dual-loop clock and data recovery (CDR) scheme. The new CDR scheme uses digital approach and solves conflict between high quality phase tracking accuracy and environment noise. It combines sigma-delta quantization noise shaping technique with the narrow-band filtering characteristic of a phase-locked loop (PLL) to suppress quantization phase noise efficiently. At the same time, it adopts the idea of fractional-N synthesizers to adjust the phase of clock signal. The new CDR prototype has been realized and tested using Cyclone-series FPGA chip to accomplish CDR function for STM-1 interface (155.52Mbit/s) and it has been applied to network equipments of SDH transport network successfully. The jitter tolerance performance exceeds STM-1 jitter specification in ITU-T Recommendation G.825 by 0.3UI at high frequency part