The TinyCAN: an optimized CAN controller IP for FPGA-based platforms

This paper presents the TinyCAN, a resource constrained controller area network controller implemented in VHDL language. The core description is fully synthesizable and fits in a FPGA-based platform occupying a maximum of 366 look-up tables. An enhanced error control strategy was elaborated with the aim of producing a more suitable behavior for safety-critical applications. For all that, compatibility with off-the-shelf components was preserved implementation details and comments on design decisions are given. The paper also presents some guidelines for the use of the proposed CAN controller IP for time-triggered architectures