A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes

Author

Lee, Se-Joong ; Kim, Kwanho ; Kim, Hyejung ; Cho, Namjun ; Yoo, Hoi-Jun

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon

Volume

1

fYear

2006

fDate

6-10 March 2006

Abstract

An on-chip interconnect is implemented with 3Gbps/wire bandwidth performance with 8:1 serialization scheme. Such high-speed serialization is achieved using a novel serialization scheme, wave-front-train. In order to apply such high-speed link technique to network-on-chip channels, three adaptive control schemes are used: supply voltage dependent reference voltage control, phase compensation scheme with self-calibrating function, and adaptive bandwidth control. The chip is fabricated using 0.18mum CMOS technology

Keywords

CMOS digital integrated circuits; adaptive control; high-speed integrated circuits; integrated circuit interconnections; network-on-chip; reference circuits; voltage control; 0.18 micron; 3 Gbit/s; CMOS technology; adaptive bandwidth control; network-on-chip; on-chip interconnect; phase compensation; reference voltage control; wave-front-train; Adaptive control; Bandwidth; CMOS technology; Clocks; Frequency synchronization; Network-on-a-chip; Propagation delay; Timing; Voltage control; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 2006. DATE '06. Proceedings

Conference_Location

Munich

Print_ISBN

3-9810801-1-4

Type

conf

DOI

10.1109/DATE.2006.243986

Filename

1656850