Title :
A hybrid framework for design and analysis of fault-tolerant architectures
Author :
Bhaduri, Debayan ; Shukla, Sandeep ; Coker, Deji ; Taylor, Valerie ; Graham, Paul ; Gokhale, Maya
Author_Institution :
Virginia Tech., Blacksburg, VA
Abstract :
It is anticipated that self assembled ultra-dense nanomemories will be more susceptible to manufacturing defects and transient faults than conventional CMOS-based memories, thus the need exists for fault-tolerant memory architectures. The development of such architectures will require intense analysis in terms of achievable performance measures- power dissipation, area, delay and reliability. In this paper, we propose and develop a hybrid automation framework, called HMAN, that aids the design and analysis of fault-tolerant architectures for nanomemories. Our framework can analyze memory architectures at two different levels of the design abstraction, namely the system and circuit levels. To the best of our knowledge, this is the first such attempt at analyzing memory systems at different levels of abstraction and then correlating the different performance measures. We also illustrate the application of our framework to self-assembled crossbar architectures by analyzing a hierarchical fault-tolerant crossbar-based memory architecture that we have developed
Keywords :
CMOS memory circuits; fault tolerance; logic design; memory architecture; nanoelectronics; self-assembly; CMOS-based memories; fault-tolerant architectures; hybrid memory analyzer; memory architecture; nanomemories; self-assembled crossbar architectures; Area measurement; Circuit faults; Delay; Fault tolerance; Manufacturing; Memory architecture; Performance analysis; Power dissipation; Power measurement; Self-assembly;
Conference_Titel :
Design, Automation and Test in Europe, 2006. DATE '06. Proceedings
Conference_Location :
Munich
Print_ISBN :
3-9810801-1-4
DOI :
10.1109/DATE.2006.244179