Title :
Using conjugate symmetries to enhance gate-level simulations
Author :
Maurer, Peter M.
Author_Institution :
Dept. of Comput. Sci., Baylor Univ., Waco, TX
Abstract :
State machine based simulation of Boolean functions is substantially faster if the function being simulated is symmetric. Unfortunately function symmetries are comparatively rare. Conjugate symmetries can be used to reduce the state space for functions that have no detectable symmetries, allowing the benefits of symmetry to be applied to a much wider class of functions. Substantial improvements in simulation speed, from 30-40% have been realized using these techniques
Keywords :
Boolean functions; logic design; logic gates; Boolean functions; conjugate symmetries; gate-level simulations; state machine; state space; Algorithms; Boolean functions; Circuit simulation; Computational modeling; Computer science; Computer simulation; Design automation; Digital circuits; Hypercubes; State-space methods;
Conference_Titel :
Design, Automation and Test in Europe, 2006. DATE '06. Proceedings
Conference_Location :
Munich
Print_ISBN :
3-9810801-1-4
DOI :
10.1109/DATE.2006.244010