Title :
A compact model to identify delay faults due to crosstalk
Author :
Rossello, Jose L. ; Segura, Jaume
Author_Institution :
Electron. Technol. Group, Univ. de les Illes Balears, Palma de Mallorca
Abstract :
In this work we present an analytical formulation to estimate quickly and accurately the impact of crosstalk induced delay in submicron CMOS ICs gates taking into account time skew. Crosstalk delay is computed from the additional charge injected from the aggressor gate on the victim gate during simultaneous switching. The model provides a very good agreement with HSPICE simulations for a 0.18 mum technology
Keywords :
CMOS logic circuits; fault simulation; logic gates; logic testing; 0.18 micron; CMOS integrated circuit gates; aggressor gate; crosstalk induced delay; delay fault identification; CMOS technology; Capacitance; Computational modeling; Crosstalk; Delay effects; Delay estimation; Fault diagnosis; Integrated circuit interconnections; Propagation delay; Semiconductor device modeling;
Conference_Titel :
Design, Automation and Test in Europe, 2006. DATE '06. Proceedings
Conference_Location :
Munich
Print_ISBN :
3-9810801-1-4
DOI :
10.1109/DATE.2006.243805
