Title :
Efficient Unknown Blocking Using LFSR Reseeding
Author :
Wang, Seongmoon ; Balakrishnan, Kedarnath J. ; Chakradhar, Srimat T.
Author_Institution :
NEC Labs. America, Princeton, NJ
Abstract :
This paper presents an efficient method to block unknown values from entering temporal compactors. The control signals for the blocking logic are generated by an LFSR. The proposed technique minimizes the size of the LFSR by propagating only one fault effect for each fault and balancing the number of specified bits in each control pattern. The linear solver to find seeds of the LFSR intelligently chooses a solution such that the impact on test quality is minimal. Experimental results show that sizes of control data for the proposed method are smaller than prior work and run time of the proposed method is several orders of magnitude smaller than that of prior work. Hardware overhead is very low
Keywords :
automatic test equipment; built-in self test; logic circuits; shift registers; value engineering; BIST; LFSR reseeding; block unknown values; blocking logic; built in self test; control signals; efficient unknown blocking; hardware overhead; linear feedback shift register; linear solver; test quality; Built-in self-test; Compaction; Hardware; Logic design; Logic gates; Observability; Signal generators; Size control; Testing; XML;
Conference_Titel :
Design, Automation and Test in Europe, 2006. DATE '06. Proceedings
Conference_Location :
Munich
Print_ISBN :
3-9810801-1-4
DOI :
10.1109/DATE.2006.243929