Title :
Automatic generation of operation tables for fast exploration of bypasses in embedded processors
Author :
Park, Sanghyun ; Shrivastava, Aviral ; Dutt, Nikil ; Earlie, Eugene ; Nicolau, Alex ; Paek, Yunheung
Author_Institution :
Dept. of Electr. Eng., Seoul Nat. Univ., Seoul
Abstract :
Customizing the bypasses in an embedded processor uncovers valuable trade-offs between the power, performance and the cost of the processor. Meaningful exploration of bypasses requires bypass-sensitive compiler. Operation tables (OTs) have been proposed to perform bypass-sensitive compilation. However, due to lack of automated methods to generate OTs, OTs are currently manually specified by the designer. Manual specification of OTs is not only an extremely time consuming task, but is also highly error-prone. In this paper, we present AutoOT, an algorithm to automatically generate OTs from a high-level processor description. Our experiments on the Intel XScale processor model running MiBench benchmarks demonstrate that AutoOT greatly reduces the time and effort of specification. Automatic generation of OTs makes it feasible to perform full bypass exploration on the Intel XScale and thus discover interesting alternate bypass configurations in a reasonable time. To further reduce the compile-time overhead of OT generation, we propose another novel algorithm, AutoOTDB. AutoOTDB is able to cut the compile-time overhead of OT generation by half
Keywords :
embedded systems; high level synthesis; microprocessor chips; AutoOT generation; AutoOTDB; Intel XScale processor model; MiBench benchmarks; automatic operation table generation; bypass configurations; embedded processors; high-level processor description; Costs; Embedded system; Energy consumption; Hazards; Performance evaluation; Pipelines; Processor scheduling; Registers; Time to market; Wiring;
Conference_Titel :
Design, Automation and Test in Europe, 2006. DATE '06. Proceedings
Conference_Location :
Munich
Print_ISBN :
3-9810801-1-4
DOI :
10.1109/DATE.2006.244047