Title :
What lies between Design Intent Coverage and Model Checking?
Author :
Das, Sayantan ; Basu, Prasenjit ; Dasgupta, Pallab ; Chakrabarti, P.P.
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur
Abstract :
Practitioners of formal property verification often work around the capacity limitations of formal verification tools by breaking down properties into smaller properties that can be checked on the sub-modules of the parent module. To support this methodology, we have developed a formal methodology for verifying whether the decomposition is indeed sound and complete, that is, whether verifying the smaller properties on the submodules actually guarantees the original property on the parent module. In practice, however designers do not write properties for all modules and thereby our previous methodology was applicable to selected cases only. In this paper we present new formal methods that allow us to handle RTL blocks in the analysis. We believe that the new approach will significantly widen the scope of the methodology, thereby enabling the validation engineer to handle much larger designs than admitted by existing formal verification tools
Keywords :
circuit CAD; formal verification; logic design; RTL blocks; design intent coverage; formal property verification; formal verification tools; model checking; Acoustical engineering; Chip scale packaging; Computer science; Design engineering; Design methodology; Formal verification; Humans; Logic;
Conference_Titel :
Design, Automation and Test in Europe, 2006. DATE '06. Proceedings
Conference_Location :
Munich
Print_ISBN :
3-9810801-1-4
DOI :
10.1109/DATE.2006.244051