PLL-Based Synchronization of Dither-Modulation Data Hiding

A new approach to synchronization recovery for signals watermarked using the dither modulation data hiding scheme is presented. The strategy followed involves the use of a digital phase-locked loop to track the offsets applied by an attacker to the sampling grid of the watermarked signal. The main element in this synchronization loop is the timing error detector which is responsible for generating an error signal, used to update the estimates of the applied offsets. It is shown how a timing error detector which has been used in digital communications may be easily adapted to extract timing information from DM watermarked signals. The performance of the proposed synchronizer is evaluated using the probability of decoding error under different models for the sampling grid offsets