Harmonic Balance Technique in Context of Functional Hardware Verification

This paper describes problems related to verification of communication systems and demonstrates approach of digital and harmonic balance co-simulation. Functional verification has become major component of digital hardware designs. Usage of analog behavioral models and co-simulation allows end-to-end simulation and verification of digital communication links. Simulation speed and ability to represent relevant design details are of paramount importance for simulation tools for RF/MW. Third distinct feature is usage of wide spread languages like VHDL-AMS or Verilog-AMS for analog part modeling