DocumentCode
460307
Title
Deep Depletion SOI Power Devices
Author
Napoli, E.
Author_Institution
Dept. of Electron. & Telecommun. Eng. Electron. & Telecommun. Eng., Napoli Univ.
Volume
1
fYear
2006
fDate
27-29 Sept. 2006
Firstpage
3
Lastpage
12
Abstract
The paper presents an innovative design concept for SOI lateral power devices that exploits the deep depletion of the substrate to dynamically increase the voltage rating of SOI devices. Numerical simulations of the device and experimental results demonstrate that the proposed physical effect is a viable way to design a whole new class of lateral power devices
Keywords
power MOSFET; semiconductor device breakdown; silicon-on-insulator; deep depletion; power semiconductor devices; semiconductor device breakdown; silicon-on-insulator; Consumer electronics; Epitaxial layers; Isolation technology; Logic design; Logic devices; Low voltage; Power electronics; Power integrated circuits; Silicon on insulator technology; Thermal resistance; Power MOSFETs; power semiconductor devices; semiconductor device breakdown; silicon on insulator (SOI) technology; switching transient;
fLanguage
English
Publisher
ieee
Conference_Titel
International Semiconductor Conference, 2006
Conference_Location
Sinaia
Print_ISBN
1-4244-0109-7
Type
conf
DOI
10.1109/SMICND.2006.283922
Filename
4063149
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