Cost-effective sampling clock synchronisation scheme with its implementation in optical orthogonal frequency division multiplexing systems

A cost-effective scheme for sampling clock synchronisation based on the interpolation algorithm is proposed and implemented via field programmable gate array (FPGA). This scheme can provide a simpler and more economical achievement than the schemes that utilise expensive external clock recovery circuits. Low system complexity is another advantage of the proposed scheme due to the utilisation of the results of the frame synchronisation. Besides, a novel fractional sampling interval calculating algorithm which aims to calculate the fractional sampling time offset in a sampling interval is also proposed and this simpler operation algorithm based on least squares method is proved to fully satisfy the multi-subcarrier characteristic of orthogonal frequency division multiplexing (OFDM) symbol. The design and experimental results of a 2.5 Gb/s FPGA-based optical OFDM receiver by using the scheme that was proposed earlier are presented here. A major improvement in this scheme for sampling clock synchronisation is demonstrated to be suitable for practical application.